1. Field of the Invention
The present invention relates to a source driver for use in a liquid crystal display device, and more specifically, to a time-division multiplexing source driver.
2. Description of Prior Art
With a rapid development of monitor types, novel and colorful monitors with high resolution, e.g., liquid crystal displays (LCDs), are indispensable components used in various electronic products such as monitors for notebook computers, personal digital assistants (PDAs), digital cameras, and projectors. The demand for the novelty and colorful monitors has increased tremendously. A Low Temperature Poly-Silicon Liquid Crystal Display (LTPS LCD) panel, on account of high resolution demands, is widely applied to various electronic devices.
Liquid crystal display (LCD) device comprises an LCD panel, a gate driver and a source driver. When the gate driver outputs a scanning signal, the source driver outputs a corresponding data signal to pixels of the LCD panel, in sequence to charge each pixel to needed voltages so as to display various grey levels.
Please refer to FIG. 1. FIG. 1 is a functional block diagram of a prior art. The source driver 5 comprises an output stage circuit 51, a digital-to-analog converter (DAC) 52, a level shifter 53, a holding latch circuit 54, a sampling latch circuit 55, and a shift register 56. The shift register 56 continuously shifts external pulses in accordance with cycles of a clock signal CLK. The sampling latch circuit 55, according to the shifted clock signal from each output of the shift register 56, simultaneously samples inputted data signals D00P/N˜D02P/N, D10P/N˜D102P/N, D20P/N˜D22P/N. The holding latch circuit 54 locks the data signal sampled by the sampling latch circuit 55 and then outputs previously sampled data signal at the same time. The level shifter 53 raises the voltage levels of data signals outputted by the holding latch circuit 54. The digital-to-analog converter 52 alters a digital data signal to a corresponding analog voltage. Control signals STB are fed into the holding latch circuit 54 and the output stage circuit 51, respectively. When the control signal STB is at rising edge, the data is fed into the holding latch circuit 54 from the sampling latch circuit 55. When the control signal STB is at falling edge, the output stage circuit 51 outputs the analogical voltage to each data line so as to drive the pixels of the LCD panel.
Since the source driver 5 is comprised transistors and signal lines, the design for the minimum size of display area is conditioned by the size of the transistors and the number of signal lines. Conventionally, the sampling latch circuit 55 and the holding latch circuit 54 require more transmission lines. Take 6-bit serial image data for RGB pixels for example, the sampling latch circuit 55 and the holding latch circuit 54 require 18 transmission lines for transmission of sampling data and latch data. Excessive transmission lines may result in an increment of layout area of the source driver 5, but also derive more coupling parasitic capacitors and resulting in extra power consumption.